The Tessent suite offers a range of different tools for introducing on-chip testing and self-testing of combinational logic circuits.

The Tessent flow includes a range of different tools, which can be divided into two main groups:

• Software suite for testing and evaluating testability of logic, memory, and analog/digital devices, analyzing tests, and increasing yield
• Solutions for adding hardware blocks to an on-chip system for analysis and self-testing.

Tessent Test Solutions

Tessent combines families of best-in-class solutions for each discipline into a unified flow to achieve 100% whole-chip coverage.

Tessent Solutions

Logic testing

Mentor Graphics offers the industry's most powerful suite of logic testing solutions with more than two decades of success testing thousands of batches of chips using compression and vectorless approaches.

Memory testing

Tessent's memory testing solutions provide extensive testing and diagnostic capabilities to meet the requirements for new manufacturing technologies, as well as for memory block analysis and self-repair.

Testing of analog/digital devices

Tessent A/D solutions are not tied to specific chip manufacturers or test equipment and are designed to address the growing number of SerDes interfaces and PLLs in today's on-chip system designs

Evaluation of manufactured ICs

The Tessent suite includes products to increase productivity during chip validation and volume production, providing solutions for testing, characterization, yield analysis and failure analysis.

Tessent Connect

Tessent Connect reduces the time and cost of DFT implementation by optimally automating within the Tessent Shell for hierarchical projects.

Built-in analytics

Tessent® Embedded Analytics is a suite of IP blocks and software for security and functional reliability, field and lab monitoring and performance optimization as well as process tuning and debugging. Our portfolio includes configurable hardware blocks for cybersecurity and reliability, non-intrusive core-logic monitoring blocks, transaction-aware monitoring of main buses and connections, IP blocks for fast data transfer to acquire and record large volumes of data, and software for processing and analyzing this data.

Key product features

• IP blocks for monitoring and analytics
• Supplied as parameterizable blocks
• Hardware cybersecurity
• Instant detection of abnormal behavior
• Mitigating and preventing the spread of threats
• Data retention, threat profile definition
• Functional reliability
• Not bound to specific manufacturers
• Verification and validation for compliance with standards
• Continuous performance optimization
• Data centers, storage facilities, etc.
• Preventive maintenance / failure analysis
• Powerful development environment and analytical software
• Support for optimization for different CPUs
• Data visualization and analysis
• Bus monitoring with protocol information
• AXI, ACE, ACElite, OCP, CHI etc.
• Rich messaging infrastructure
• On- and off-chip interfaces
• Support for vendor debugging systems (CoreSight, PDTrace)
• IEEE1149, SWD-style, Aurora, SerDes, USB2
• Ethernet, PCIe, USB3