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Full range of tools covering the entire electronic system development cycle
Official supplier of Siemens EDA (Mentor Graphics) and other leading EDA tools for IC and PCB design, verification, and manufacturing.
Full range of tools covering the entire electronic system development cycle
application is designed to explore, verify and virtually prototype SoC architecture at the system level. It is based on the TLM 2.0 transaction engine. Vista enables SoC developers to make the best design architecture se
Visual Elite is a project development and integration environment that allows developers and system architects to create SoC and subsystem designs based on blocks implemented in SystemC, TLM 2.0 and HDL. The core of Visu
The Catapult HLS application is designed to create SoC projects at the ANSI C++ and SystemC standard description level and then implement them at the RTL level. Catapult HLS performs automatic RTL synthesis based on a hi
Questa transforms the functional verification process, dramatically increasing its productivity and resource management efficiency. Based on several advanced technologies and integration with the Veloce hardware emulatio
Questa InFact is designed to generate portable test effects. It increases the level of verification abstraction and allows users to automatically generate different scenarios for unit, subsystem and SoC-level testing. Bu
The Questa Formal suite of applications complements traditional RTL code modeling by formally analyzing object behavior to detect possible states that might lead to an error. This approach identifies errors that were mis
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