application is designed to explore, verify and virtually prototype SoC architecture at the system level. It is based on the TLM 2.0 transaction engine. Vista enables SoC developers to make the best design architecture selection decision and begin debugging and validating hardware and software. This task is accomplished by analyzing, debugging, and prototyping individual solutions at the system level, even before the development of the project's RTL code, which shortens the development cycle and increases the likelihood of successful project completion without additional costly iterations.

Mode SoCs in networking, memory, and multicore applications are becoming increasingly complex, making the choice of one or another architectural solution one of the most critical steps in the entire development cycle, directly affecting the end result and competitiveness. One of the critical tasks is the configuration of the hardware and software architecture of multicore processors and interconnect buses, which directly affects the bus bandwidth and overall system performance.

Vista includes a system-level modeling apparatus, a built-in library of reconfigurable blocks, an intuitive graphical editor for "building" the system, and tools for analyzing and debugging hardware and software solutions.

Individual system block models can be optimized by reconfiguring their micro-architecture, interconnect buses, and memory hierarchy. Vista uses a unique timing analysis mechanism that allows different bus configurations and processing protocols to be quickly tested without affecting the overall functioning of the system. Developers have the ability to optimize performance and power consumption from the highest level of approximation of the system architecture to the selection of specific bus and protocol implementations. To control the movement of data, special objects (data packets) are tagged with code labels so that it is possible to accurately "trace" the movement of data across the buses and to make optimal decisions about the choice of bus architecture and protocols.

Developers can perform statistical simulations of bus throughput with arbitrary traffic and traffic driven by a real program running on a CPU model.

Vista has a powerful set of tools for examining and analyzing various performance and power consumption characteristics, including analysis of peak loads, average packet latency and bus throughput, as well as load on any port, bus or subsystem.

Vista allows you to quickly prototype a system based on basic blocks and analyze performance and power consumption changes depending on the chosen system architecture and load level. The use of scalable models at different levels ensures optimized performance and power consumption at all levels of design presentation from conceptual to RTL code implementation. This allows you to optimize the design in silicon, provide the required performance at any load and provide the ability to easily modify the architecture when transitioning to a new generation of SoCs with higher requirements.

Main advantages of Vista

• Analysis of performance and power consumption in the early stages of design
• Minimizing risks and improving design quality
• Managing and optimizing performance and power consumption throughout the design cycle
• In-depth understanding of the properties of the basic algorithms for scaling a project
• Using scaling with predictable and controllable results

Main features of Vista

• Built-in library of configurable architecture blocks based on TLM 2.0 - CPU, Bus (AXI, AHB), Memory, Cache, DMAC, INTC and others
• Functional modeling at the system level with the ability to analyze statistical results
• Control the movement of data packets, states and attributes of models
• TLM 2.0 Model Builder
• Support for hardware and software verification, including processor models and debugging tools
• Debugging and status monitoring of SystemC and TLM 2.0 models
• Advanced visualization and report generation capabilities
• Ability to analyze performance, power consumption, latency, utilization and current state