Functional Verification

Symphony

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Symphony is the industry's fastest and most flexibly configurable mixed analog-to-digital functional simulation system, designed to accurately verify test object function, performance and connectivity in both block and hierarchical modes, across the full range of analog-to-digital ICs of any application. The modular architecture of Symphony includes an AFS (Analog FastSPICE) application for mixed design simulation with the accuracy of a standard Spice simulation and over 20 million pins. Symphony provides, on average, twice the simulation speed of its predecessor generation systems. The application has been tested on a wide range of mixed-signal analog-to-digital ICs and their individual blocks, including ADCs, transceivers, power management circuits, multi-GHz PLL/DLL circuits, SerDes circuits, and sensors.

The unique optimization algorithm automatically tunes to the specific architecture and topology of your design, resulting in high performance analog-to-digital verification designs. Symphony is fully integrated with Solido Variation Designer, the leading tool for variation-aware system design. Together, Solido Symphony provides fast and accurate verification of such systems at the block level and complex IC designs. The verification process includes outputting results in the form of statistical evaluation tables derived from a small amount of time and amount of testing, with an accuracy close to full-scale testing at the Spice level.

Fastest and most accurate simulation of mixed analog-to-digital projects

  • Takes full advantage of the AFS
  • Spice-level accuracy certified by major foundries
  • The simulation kernel runs 5-10 times faster than traditional Spice simulators
  • Simulation kernel runs 2-6 times faster than Spice simulators with parallel processing

Fully configurable architecture

  • The architecture of the application is customized to the specific project to get the desired result
  • Supports all standard digital modeling systems
  • Maximum reuse of verification infrastructure
  • Integration with all standard circuit editors

Best-in-class application versatility

  • Supports mostly mixed analog-digital projects
  • Ability to reuse A/D command line arguments
  • Comprehensive support for A/D boundary elements
  • Increased productivity of verification through the ability to save the state of the simulation process and restart from a checkpoint

Additional verification and debugging options

  • High Hi-Z impedance detection capability in mixed simulation mode
  • Integration with Solido Variation Designer
  • Noise analysis in transient simulation
  • Built-in visualizer with contextual cross-references during debugging
  • Interactive TCL mode during debugging

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